Content-Addressable Memory (CAM) References

This article is a listing of references in the field of content-addressable memory with a focus on circuit design. Some networking papers are included that explain the applications where CAM are used. This list is now old as I have not been following CAM development for a few years now.

For an introduction to content-addressable memory architecture and circuits, see my CAM Primer. For a more comprehensive introduction, please see my paper titled: Content-addressable memory (CAM) circuits and architectures: A tutorial and survey.

Table of Contents

General CAM

Content-Addressable Memory Wikipedia Entry

R. Panigrahy and S. Sharma. Sorting and searching using ternary CAMs. IEEE Micro, 23(1):44-53, January-February 2003.

S. Azgomi. Using content-addressable memory for networking applications. World Wide Web, http://www.commsdesign.com/main/1999/11/9911feat3.htm, 1999.

S. Stas. Associative processing with CAMs. In Northcon/93 Conference Record, pages 161-167, 1993.

I.N. Robinson. Pattern-addressable memory. IEEE Micro, 12(3):20-30, June 1992.

L. Chisvin and R.J. Duckworth. Content-addressable and associative memory: Alternatives to the ubiquitous RAM. IEEE Computer, 22(7):51-64, July 1989.

CAM Circuits (Selected Papers)

K. Pagiamtzis and A. Sheikholeslami, Using cache to reduce power consumption in content-addressable memories (CAMs), in IEEE Custom Integrated Circuits Conference (CICC), September 2005, pp. 369–372. (PDF, BibTeX)
[Abstract]

I. Arsovski and R. Nadkarni, Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines, in IEEE Custom Integrated Circuits Conference (CICC), September 2005, pp. 447–450.

B.-D. Yang and L.-S. Kim, A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver, IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1736–1744, August 2005.
[IEEE Xplore entry]

S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router, IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 853–861, April 2005. [IEEE Xplore entry]

J.-S. Wang, H.-Y. Li, C.-C. Chen, C. Yeh, An AND-type match-line scheme for energy-efficient content addressable memories, in IEEE Solid-State Circuits Conference (ISSCC), February 2005, pp. 464–465, 610.
[IEEE Xplore entry]

H. Noda, K. Inoue, M. Kuroiwa, F. Igaue, K. Yamamoto, H.J. Mattausch, T. Koide, A. Amo, A. Hachisuka, S. Soeda, I. Hayashi, F. Morishita, K. Dosaka, K. Arimoto, K. Fujishima, K. Anami, and T. Yoshihara, A cost-efficient high-performance dynamic TCAM with pipelined hierarchical search and shift redundancy architecture, IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 245–253, January 2005. [IEEE Xplore entry]

K. Pagiamtzis and A. Sheikholeslami, A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme, IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1512–1519, September 2004. (PDF, BibTeX)
[Abstract, Citations & References] [IEEE Xplore entry] [CiteSeer entry]

S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, A dynamic CAM-based on a one-hot-spot block code–for millions-entry lookup, in IEEE VLSI Circuits Symposium, June 2004, pp. 382–385. [IEEE Xplore entry]

H. Noda, K. Inoue, M. Kuroiwa, A. Amo, A. Hachisuka, H.J. Mattausch, T. Koide, S. Soeda, K. Dosaka, and K. Arimoto, A 143MHz 1.1W 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture, in IEEE Solid-State Circuits Conference (ISSCC), February 2004, pp. 208–209, 523. [IEEE Xplore entry]

K. Pagiamtzis and A. Sheikholeslami, Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories, in IEEE Custom Integrated Circuits Conference (CICC), September 2003, pp. 383–386. (PDF, BibTeX)
[Abstract, Citations & References] [IEEE Xplore entry] [CiteSeer entry] [Google Scholar Citations]

C.S. Line, J.C. Chang, and B.D. Liu. A low-power precomputation-based fully parallel content-addressable memory. IEEE Journal of Solid-State Circuits, 38(4):654-662, April 2003.

I. Arsovski and A. Sheikholeslami. A current-saving match-line sensing scheme for content-addressable memories. In IEEE International Solid-State Circuits Conference Technical Digest, pages 304-305,494, 2003.

I. Arsovski, T. Chandler, and A. Sheikholeslami. A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme. IEEE Journal of Solid-State Circuits, 38(1):155-158, January 2003.

A. Efthymiou and J.D. Garside. An adaptive serial-parallel CAM architecture for low-power cache blocks. In International Symposium on Low Power Electronics and Design, pages 136-141, 2002.

I.Y.L. Hsiao, D.H. Wang, and C.W. Jen. Power modeling and low-power design of content addressable memories. In Proceedings of the IEEE International Symposium on Circuits and Systems, volume 4, pages 926-929, 2001.

H. Miyatake, M. Tanaka, and Y. Mori. A design for high-speed low-power CMOS fully parallel content-addressable memory macros. IEEE Journal of Solid-State Circuits, 36(6):956-968, June 2001.

F. Shafai, K.J. Schultz, G.F.R. Gibson, A.G. Bluschke, and D.E. Somppi. Fully parallel 30-MHz, 2.5-Mb CAM. IEEE Journal of Solid-State Circuits, 33(11):1690-1696, November 1998.

M.M. Khellah and M.I. Elmasry. Use of charge sharing to reduce energy consumption in wide fan-in gates. In Proceedings of the IEEE International Symposium on Circuits and Systems, volume 2, pages 9-12, 1998.

C.A. Zukowski and S.Y. Wang. Use of selective precharge for low-power content-addressable memories. In Proceedings of the IEEE International Symposium on Circuits and Systems, volume 3, pages 1788-1791, 1997.

CAM and Networking

M.A. Ruiz Sanchez, E.W. Biersack, and W. Dabbous. A survey and taxonomy of IP lookup algorithms. IEEE Network, 15(2):8-23, March-April 2001.

P. Gupta, S. Lin, and N. McKeown. Routing lookups in hardware at memory access speeds. In Proceedings of the Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies, INFOCOM`98, volume 3, pages 1240-1247, 1998.

A.J. McAuley and P. Francis. Fast routing table lookup using CAMs. In Proceedings of IEEE Infocom, volume 3, pages 1282-1391, 1993 (CiteSeer entry).

T.-B. Pei and C. Zukowski. Putting routing tables in silicon. IEEE Network Magazine, 6(1):42-50, January 1992.

General RAM Papers

P. Shivakumar and N.P. Jouppi. CACTI 3.0: An integrated cache timing, power, and area model. Technical Report WRL Research Report 2001/12, Digital Equipment Corporation Western Research Lab, 2001.

S.J.E. Wilton and N.P. Jouppi. CACTI: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits, 31(5):677-688, May 1996 (CiteSeer entry).

B.S. Amrutur and M.A. Horowitz. Speed and power scaling of SRAM's. IEEE Journal of Solid-State Circuits, 35(2):175-185, February 2000 (CiteSeer entry).

G. Reinman and N.P. Jouppi. CACTI 2.0: An integrated cache timing and power model. Technical Report WRL Research Report 2000/07, Digital Equipment Corporation Western Research Lab, 2000.

S.J.E. Wilton and N.P. Jouppi. An access and cycle time model for on-chip caches. Technical Report WRL Research Report 93/5, Digital Equipment Corporation Western Research Lab, 1994.

T. Wada, S. Rajan, and S.A. Przybylski. An analytical access time model for on-chip cache memories. IEEE Journal of Solid-State Circuits, 27(8):1147-1156, August 1992.

Priority Encoders

C.H. Huang, J.S. Wang, and Y.C. Huang. Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques. IEEE Journal of Solid-State Circuits, 37(1):63-76, January 2002.

J.-S. Wang and C.-H. Huang. High-speed and low-power CMOS priority encoders. IEEE Journal of Solid-State Circuits, 35(10):1511-1514, October 2000.

J.S. Wang and C.H. Huang. High-speed single-phase-clocked CMOS priority encoder. In Proceedings of the IEEE International Symposium on Circuits and Systems, volume 5, pages 537-540, 2000.