Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories

K. Pagiamtzis and A. Sheikholeslami, “Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories,” in IEEE Custom Integrated Circuits Conference (CICC), September 2003, pp. 383–386.

• Download PDF
• BibTeX
• IEEE Xplore
• Google Scholar list of citations

Abstract

This paper presents a pipelined match-line and a hierarchical search-line architecture to reduce power in content-addressable memories (CAM). The overall power reduction is 60%, with 29% contributed by the pipelined match-lines and 31% contributed by the hierarchical search-lines. This proposed architecture is employed in the design of a 1024 x 144 bit ternary CAM, achieving 7 ns search cycle time at 2.89 fJ/bit/search in a 0.18 μm CMOS process.