Using cache to reduce power consumption in content-addressable memories (CAMs)

K. Pagiamtzis and A. Sheikholeslami, “Using cache to reduce power consumption in content-addressable memories (CAMs),” in IEEE Custom Integrated Circuits Conference (CICC), September 2005, pp. 369–372.

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Abstract

We propose using caching to save power in content-addressable memories (CAMs). By using a small cache along with the CAM, we avoid accessing the larger and higher power CAM. For a cache hit rate of 90%, the cache-CAM (C-CAM) saves 80% power over a conventional CAM, for a cost of 15% increase in silicon area. Even at a low hit rate of 50%, a power savings of 40% is achieved. The proposed C-CAM is employed in the design of a testchip demonstrating a 2.6 fJ/bit/search in a 0.18 μm CMOS process.